(1) Field of the Invention
The invention relates to a method of planarizing an integrated circuit device, and more particularly, to a method of planarizing a submicron integrated circuit device by integrating a plasma-enhanced silicon oxide deposition, a TEOS with ozone silicon oxide deposition and a spin-on-glass deposition process.
(2) Description of the Prior Art
In conventional planarization of the metallurgy-dielectric layers of an integrated circuit, a metal is deposited and patterned by conventional lithography and etching techniques. Then the intermetal dielectric layer, which is typically silicon oxide material, is formed thereover. The dielectric layer may now be etched back to planarize the metallurgy-dielectric layers. There are basic problems in planarizing the metallurgy-dielectric layers wherein there are both wide spaces, greater than 0.6 microns, and narrow spaces, less than 0.6 microns. Conventional planarization methods have difficulty filling all spaces satisfactorily.
A number of patents have addressed these and other problems in planarization. U.S. Pat. No. 5,250,472 to K. C. Chen and S. T. Hsia describes an integration of a partial etchback siloxane spin-on-glass process with a silicate spin-on-glass process. U.S. Pat. No. 4,962,063 to Maydan et al involves a plasma deposition followed by flowing of a low melting point glass to provide a planarized surface. In their paper, "SACVD: A New Approach for 16Mb Dielectrics"(J. G. Lee, S. H. Choi, T. C. Ahn, C. G. Hong, P. Lee, K. Law, M. Galiano, P. Keswick, and B. Shin, Semiconductor International, May 1992, pp. 116-120), the authors discuss the use of sub-atmospheric chemical vapor deposition of TEOS-ozone undoped silicate glass and borophosphosilicate glass.